ASIC / FPGA Design

Sivaltech ASIC/FPGA Design team has been providing end to end services to our customers on design, verification, physical design, post silicon validation.

SOC Design & Implementation

  • RTL Design
  • Micro-architecture Devising
  • CDC / Lint / Formal

IP / SOC Verification

  • Functional & Code Coverage
  • System Verilog / Verilog
  • UVM / OVM

Physical Design

  • Implementation from RTL till Chip Finish
  • High Speed Low Power Design with Multi-million Gate
  • Timing / Reliability / Testability / Manufacturability

Post Silicon Validation

  • Post-silicon and Bring-up
  • Validation and Debug
  • Firmware


  • Proven capability of delivering on different aspects of IP and SOC design flow
  • Expertise in SOC Integration, Synthesis, Lint, CDC, STA,Low Power
  • Ability to handle Micro-architecture level planning and enactment
  • Proficiency on Latest Flows, Environments and Practices
  • Capability on High Speed and Low Power Designs

IP/SOC Verification

  • Capability on developing Scalable and ReusableTestbenches, considering reuse of IP level Verification component for SoC Level
  • Test-bench development as per DUT requirement
  • Building Complex Scoreboard, Checkers and Assertions
  • Test plan based on design specifications
    • Functional & Code Coverage Closure
    • Test case creation with constraint random verification and directed test
  • RAL Modelling
  • Low Power Verification
  • Strong Skill in System Verilog / Verilog & UVM / OVM
  • Expertise across standard verification and debug tools

Physical Design

  • RTL synthesis and Constraint Development
  • DFT Planning, Insertion and Fault Grading Services
  • Full-chip as well as Block Level Pre and Post Layout STA with Timing Budgeting
  • Hierarchical Design Planning, Partitioning with Aggressive Die size estimatio
  • Backend CAD flow along with Methodology Development and carry through
  • Expertise in Technology node as lower as 7nm and beyond with complex clock structure and UPF based Multi power domain
  • Signoff expert in Timing, Power estimation, IR & RV,LEC, CLP, DRC, LVS for Block as well as Full Chip
  • ECO Implementation and Tapeout Support

Pre & Post -Silicon

  • Bring-up
    • Expertise on FPGA and Palladium like platforms
    • Automation of test suite
    • Creation of different test pattern like Production, Characterization, and Burn-in for ATE
  • Validation and Debug
    • Using Vivado, Synplify & ProtoCompiler
    • Board level debug using Logic Analyser & Protocol Analyser
    • On ATE Boards
  • Firmware
    • Platform Specific driver development