Sivaltech aims to be a leading service provider in VLSI and Embedded Software by exceeding expectations on delivery, meeting stringent design schedules and demonstrating intelligence to tackle complex design challenges.
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sales@sivaltech.com
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USA : +1 858 939 0020
India : +91 707 557 7184
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Sivaltech ASIC/FPGA Design team has been providing end to end services to our customers on design, verification, physical design, post silicon validation.
SOC Design & Implementation
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RTL Design
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Micro-architecture Devising
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CDC / Lint / Formal
IP / SOC Verification
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Functional & Code Coverage
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System Verilog / Verilog
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UVM / OVM
Physical Design
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Implementation from RTL till Chip Finish
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High Speed Low Power Design with Multi-million Gate
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Timing / Reliability / Testability / Manufacturability
Post Silicon Validation
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Post-silicon and Bring-up
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Validation and Debug
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Firmware
Design
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Proven capability of delivering on different aspects of IP and SOC design flow
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Expertise in SOC Integration, Synthesis, Lint, CDC, STA,Low Power
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Ability to handle Micro-architecture level planning and enactment
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Proficiency on Latest Flows, Environments and Practices
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Capability on High Speed and Low Power Designs
IP/SOC Verification
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Capability on developing Scalable and ReusableTestbenches, considering reuse of IP level Verification component for SoC Level
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Test-bench development as per DUT requirement
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Building Complex Scoreboard, Checkers and Assertions
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Test plan based on design specifications
- • Functional & Code Coverage Closure
- • Test case creation with constraint random verification and directed test
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RAL Modelling
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Low Power Verification
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Strong Skill in System Verilog / Verilog & UVM / OVM
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Expertise across standard verification and debug tools
Physical Design
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RTL synthesis and Constraint Development
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DFT Planning, Insertion and Fault Grading Services
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Full-chip as well as Block Level Pre and Post Layout STA with Timing Budgeting
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Hierarchical Design Planning, Partitioning with Aggressive Die size estimatio
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Backend CAD flow along with Methodology Development and carry through
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Expertise in Technology node as lower as 7nm and beyond with complex clock structure and UPF based Multi power domain
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Signoff expert in Timing, Power estimation, IR & RV,LEC, CLP, DRC, LVS for Block as well as Full Chip
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ECO Implementation and Tapeout Support
Pre & Post -Silicon
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Bring-up
- • Expertise on FPGA and Palladium like platforms
- • Automation of test suite
- • Creation of different test pattern like Production, Characterization, and Burn-in for ATE
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Validation and Debug
- • Using Vivado, Synplify & ProtoCompiler
- • Board level debug using Logic Analyser & Protocol Analyser
- • On ATE Boards
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Firmware
- • Platform Specific driver development