Sivaltech aims to be a leading service provider in VLSI and Embedded Software by exceeding
expectations on delivery, meeting stringent design schedules and demonstrating intelligence
to tackle complex design challenges.
Sivaltech is a semiconductor services
organization that provides Digital Design, Analog Mixed Signal, Design Verification, Physical Design, DFT, and Embedded Software Solutions to some of the world’s leading semiconductor companies. The environment is fast-paced and requires daily cross-functional interaction along with good communication, planning and execution skills.
Current Openings:
Essential Duties and Responsibilities:
Planning the verification of complex digital systems
Creating a constrained-random verification environment using System Verilog and UVM
Identifying and writing all types of coverage measures for stimulus and corner-cases
Debugging tests with design engineers to deliver functionally correct design blocks
Closing coverage measures to identify verification holes and to show progress towards tape-out
Education Requirements :
Minimum Education : Bachelor’s degree in Electrical Engineering or related field
Location:
San Diego, CA
Understanding the business requirements from Sivaltech clients and defining the scope and key objectives of Sivaltech IP– 20% :
Collaborating with Sivaltech clients and other stake holders in order to understand the business background and clearly define the scope and key objectives of the project.
Developing clear statement of objectives and performance metrics.
Translating Sivaltech client needs in to business requirements into detailed analytical requirements in accordance with petitioner’s problem-solving approach.
Creating hypotheses of variable relationships relevant to that business problem.
Designing the complete Architectural Framework and spec for future versions of the IP – 20% :
Discussing the merits and demerits of various alternative analytical approaches and with respective to Sivaltech client needs.
Working with the client to finalize intermediate, final deliverables, and the timelines for the project.
Interacting with RTL Design, Verification and physical design teams inhouse to make and create sustainability report and defining achievable standards along with trade offs to meet the defined spec.
Extracting relevant data from appropriate data sources for the execution of the project.
Program Management – 25% :
Data quality check – Ensuring data integrity by cross - checking the extracted data with the relevant stakeholders for data accuracy and consistency. Maintaining an accurate check on Open source vs indigenously developed components for the IP while not breaching the open source standards and agreements.
The cndidate will work in conjunction with other team members to develop Business Process environments specification documents and modify high-level architecture of the IP.
Sync Ups with RTL design team members and regular cross verification of the architecture document with simulation environment.
Improving Sivaltech verification signoff process on a continuous basis for reusability and smooth handover to Physical design team by continuously tracking the methodology standards and updating the sign off methodology.
Managing the overall schedule and incorporating inputs from marketing teams.
Meeting clients and architecting variants of the IP– 35% :
Candidate will travel extensively meeting clients to establish business cases for Sivaltech IP variants with different foundries and technology nodes.
With sound understating of the ASIC business in US, candidate will be responsible for architecting different variants of the IP while understanding client specifications and will be responsible for embedding the same in architecture document.
Will be responsible for feasibility analysis and clearly define the standards and variants of the VIPs that needs to be developed.
Collating and presenting the recommendations and insights that would enable continuous measurable improvement in the client’s business decisions.
Preparing executive summary of the results for the senior management.
The position of Programmer Analyst is a professional and specialized occupation which requires, at a minimum, a Bachelor’s Degree in Computer Science, Computer Applications, CIS, Information Technology or related.
Essential Duties and Responsibilities: :
Planning the verification of complex digital systems
Creating a constrained-random verification environment using System Verilog and UVM
Identifying and writing all types of coverage measures for stimulus and corner-cases
Debugging tests with design engineers to deliver functionally correct design blocks
Closing coverage measures to identify verification holes and to show progress towards tape-out
Tools:
VCS, URG, Verdi, System Verilog, Verilog, UVM, DVE
Education Requirements :
Required : Bachelor's degree in Electronics Engineering
Job Function:
ASIC Physical Design implementation using IC Compiler; Logic Synthesis, I/O Pad Ring Design, Floor Planning, Placement, CTS, Routing, STA with Timing Closure in Advanced Technology Nodes.Timing closure methodology implementation and sign off, Power grid, Clock tree, and Low-power reduction Implementation methods; Signal integrity fixes with OCV/AOCV/Statistical Timing methods, Physical Verification, Conformal Equivalence Check, Conformal Lower Power (CLP), IR drop analysis, PERL, TCL Scripting for all ASIC Methodology Implementations
Minimum Education : Bachelor's deegree in Electrical Engineering
Minimum experience: Five (5) years
Position requires five (5) years of post-baccalaureate experience that is progressive in nature
Five (5) years of experience must include five (5) years of experience in: PrimeTime SI, PrimeTime PX, Design Compiler–Topographical, Synopsys Formality, RedHawk
Location:
San Diego, CA. Job may involve working at various unanticipated locations throughout the United States. Travel required to the extent of relocating to various unanticipated locations throughout the United States. Employer will conduct background check and reference check. Please send resumes referencing the aforementioned job title and reference number to Sivaltech Inc. 6170 Cornerstone Ct. E, Ste 260, San Diego CA 92121
Job Function:
Design verification engineers will likely have experience in functional or formal design verification. These candidates are expected to know the essential technical languages, disciplines, and methodologies that are generally tacked to this type of position.
Qualification Requirements :
At least 4 years of experience in ASIC verification including: Verification methodology using System Verilog, SVA, OVM/ UVM, Vera, or VMM
Experience in writing feature based test plans and implementing such test plans using one of the methodologies listed above
Experience running regressions, debugging test failures and achieving test plan targets
Knowledge in hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL
Analytic and debugging skills
Strong knowledge of digital design
Understanding of Object Oriented Programming (OOP) concepts
Experience with Gate Level Simulation, Low Power Verification, Formal Verification are preferred
Familiar with C/C++, Perl, Tcl
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Requirement details:
Write Functional and code coverage, digital design and verification of all areas of lifecycle
Plan and debug tests
h4 Development of test cases, checkers, and scoreboards
Develop a complete test bench in System Verilog with Universal Verification Methodology (UVM)
Work on simulators like Verilog Compiler Simulator (VCS)
Plan for Assertion, Coverage metrics and coverage closure to make sure designs are verified thoroughly
Digital Design and Verification (ASIC & RTL)
Work on modem processors and protocols like AHB, AXI and perform design verification on all areas of verification lifecycle
Tools:
UVM Methodology, Verilog, System Verilog
Minimum Education :
Master's degree in Electronics / Electrical Engineering Technology
Minimum experience :
[Two (2) years] Two (2) years of experience must include two (2) years of experience in: UVM Methodology, Verilog, System Verilog. Employer will conduct background check and reference check
Job Site :
San Diego, CA. Job may involve working at various unanticipated locations throughout the United States. Travel required to the extent of relocating to various unanticipated locations throughout the United States. Please send resumes referencing the aforementioned job title and reference number to Sivaltech Inc. 6170 Cornerstone Ct. E, Ste 260, San Diego CA 92121
Job Function:
RTL/Digital design engineers will design and implementation of SoC, Peripherals, Graphics, Modem, Bus and Network-on-chip cores. These candidates will understand and work on all aspects of the VLSI development cycle such as architecture, micro architecture, Synthesis/PD interaction and design convergence and actively work with various core, verification, and physical design teams across multiple sites. They will perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification.
Qualification Requirements :
4-10 years of solid experience in digital front-end design
Expertise in RTL coding in Verilog/VHDL/SV
Familiarity with various bus protocols like AHB, AXI is highly desired
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow
Experience in mobile Multimedia/Camera design is a plus
DSP /ISP knowledge is a plus
Working knowledge of timing closure is a plus
Expertise in Perl, TCL language is a plus
Expertise in post-Si debug is a plus
Good documentation skills & ability to create unit level test plans
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Job Function:
Physical design engineers are ideally creative, motivated, energetic, pleasant to work with, and put the needs of the team first. These candidates will be responsible for designs and test structures in RTL and GDSII as well as support areas regarding lint/cdc/P&R/Physical. These candidates may also participate in flow for advance process nodes ranging from 28nm and beyond. Supporting any EDA tool bench marking activities may be needed from time to time.
Qualification Requirements :
4+ years of industry experience in the following technical areas :
Physical design implementation (Floorplanning, CTS, and/or STA) in advanced technologies
STA tool and timing closure methodologies
Power grid, clock tree, and low-power reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Floorplanning, Placement, and/or CTS
Physical Verification, Conformal Low Power (CLP), IR drop analysis, and Formal Verification
Programming and scripting skills (Tcl, perl and/or C)
Clock tree analysis and optimization
Strong verbal and written communication skills
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Job Function:
DFT engineers will be responsible for DFT architecture and test methodology definition, and driving implementation primarily for Scan-based (ATPG) testing of high-end SoCs.
These candidates likely lead a team DFT design and ATPG engineers and programmers to define DFT structures and tool flows needed for testing next-generation high-end server SoC products and drive their successful implementation. In addition to work within a DFT team, these candidates will work with hardware design teams to ensure successful implementation of various DFT structures in RTL, and they will work with SoC implementation teams on synthesis, physical design, clocking, timing, and design verification.
These candidates will also work with Product and Test Engineering (PTE) teams to drive successful bring-up of test vectors on ATE platforms. This role will span from current to future SoC products, and as such candidate activities will include strategy, design, methodology, and test execution. These candidates will interface with internal tool development teams and will be responsible for driving synergies that facilitate test insertion, clock design, and vector development automation. Finally, these candidates will work with tool vendors, such as Mentor Graphics and Synopsys, to define and integrate tool capabilities (particularly DFT insertion and ATPG) needed to implement and roll out DFT strategies.
Responsibilities include: Test strategy definition, DFT Architecture for large multi-core server chips, Logic specification and RTL design of DFT IP Software specification, DFT team leadership of related activities, ATPG test planning (including coverage, test time, test memory footprint on ATE Coordinates, cross-functional front-to-back SoC implementation and verification of DFT structures), and Bring-up of ATPG patterns on ATE.
Qualification Requirements :
3+ years of experience in the following technical areas :
Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to-back SoC implementation flows
Test vector planning for bring-up and production, and hand-on ATE bring-up experience
Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small Delay Defects, Path testing, LOC/LOS, etc.
Tessent, DFTC, TCL/PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including SDF, and Advantest ATE
Architecting automation strategies that align with third party DFT tools and creating further efficiencies
Leading large DFT/ATPG teams
Defining/bring-up of DFT architecture including hierarchical core/chip based flows and pattern retargeting
Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Job Function:
Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.
Qualification Requirements :
Minimum 3 years of experience
Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
Experience with Verilog and System Verilog
RTL design experience with Perl/TCL/Makefile scripting
Experience with Power Analysis using Power Artist and PTPX
Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Job Function:
Post-Silicon validation engineers will be self-motivated and will perform post-Silicon device level and system level validation and debugging. These candidates will need to have strong SW development background and should have worked in firmware development for complex SoCs-. Working experience with ARM debugger, CoreSight, JTAG, Lauterbach Trace 32 are required. The ideal candidate should leverage their knowledge and experience to provide leadership, technical guidance, and proper execution of silicon validation
Qualification Requirements :
4+ years of experience in embedded software/silicon validation
Experience with writing and reviewing validation test plans
Experience with creating validation suite and building automation
Experience with development of directed, random, and pseudo-random diagnostics for validation in compliance with Silicon specifications
Debug of diagnostics on various platforms using JTAG, Logic Analyzers, Oscilloscopes and similar equipment will be required
Interaction with various engineering teams (e.g. systems, hardware design, design validation, software engineers, & test engineering) in test-environment bring-up & development in order to meet team goals and resolve problems in a timely, effective and professional manner will be required
ARM System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug
Experience with assembly and C programming
Have hands on experience of SOC architecture, micro-processor verification, and silicon debug environments
Hands on experience of processor programming and simulation
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
Job Function:
Post-Silicon validation engineers will be self-motivated and will perform post-Silicon device level and system level validation and debugging. These candidates will need to have strong SW development background and should have worked in firmware development for complex SoCs-. Working experience with ARM debugger, CoreSight, JTAG, Lauterbach Trace 32 are required. The ideal candidate should leverage their knowledge and experience to provide leadership, technical guidance, and proper execution of silicon validation
Qualification Requirements :
4+ years of experience in embedded software/silicon validation
Experience with writing and reviewing validation test plans
Experience with creating validation suite and building automation
Experience with development of directed, random, and pseudo-random diagnostics for validation in compliance with Silicon specifications
Debug of diagnostics on various platforms using JTAG, Logic Analyzers, Oscilloscopes and similar equipment will be required
Interaction with various engineering teams (e.g. systems, hardware design, design validation, software engineers, & test engineering) in test-environment bring-up & development in order to meet team goals and resolve problems in a timely, effective and professional manner will be required
ARM System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug
Experience with assembly and C programming
Have hands on experience of SOC architecture, micro-processor verification, and silicon debug environments
Hands on experience of processor programming and simulation
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Preferred : Master's in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX
IoT/Wearables
Job Function:
IoT/Wearables embedded systems engineers will be a part of a team of developers with expertise in low-level device driver software and HW/SW interfaces. The candidates are proficient in C, and JTAG based hardware debugger (preferably Lauterbach usage) knowledge is required. These candidates will need a very good understanding of ARMv7/ARMv8/x86 architectures and will need to know how to utilize off-target development and debugging platforms in-addition to on target development. Strong familiarity and understanding of Operating System internals, RTOS Internals and Linux Internals is very useful. These candidates will work with minimal supervision, perform task definition, and work breakdown including time estimation as well as create, document and execute detailed test plans. These candidates will work closely with hardware design engineers to successfully drive projects to completion.
Qualification Requirements :
2 - 6 years of development and test experience in embedded software and firmware
Experience in RTOS and Linux internals
Experience in ARM/x86 internals
Good working experience in using IAR/Keil development environment
Good experience in C programming
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science and / or Electrical Engineering
Preferred : Master's in Computer Engineering, Computer Science and / or Electrical Engineering
Location:
Bangalore, India & Hyderabad, India
Storage
Job Function:
Storage embedded systems engineers will be talented, motivated and experienced. These candidates will have expertise in SAS/SATA/NVMe/UFS and will need a very good understanding of SAS/SATA/NVMe/UFS protocol. These individuals need to know how to utilize off-target development and debugging platforms in-addition to on target development. Strong familiarity and understanding of Operating System internals, Linux Internals, and RTOS will be very useful. These candidates will work with minimal supervision, perform task definition, and work breakdown including time estimation as well as create, document and execute detailed test plans. These candidates will work closely with hardware design engineers to successfully drive projects to completion.
Qualification Requirements :
2 – 6 years of development and test experience in storage firmware
Experience with SAS/SATA/NVMe front end and back end firmware
Experience with SAS/SATA/NVMe protocol
Experience in FTL, Wear-levelling and garbage collection algorithms
Good working experience in using ARM developer studio
Good experience in C programming
Experience with RTOS (ThreadX) internals
Education Requirements:
Required : Bachelor's in Computer Engineering, Computer Science and / or Electrical Engineering
Preferred : Master's in Computer Engineering, Computer Science and / or Electrical Engineering
Location:
Bangalore, India & Hyderabad, India
Requirement details:
Research, analyze components and chips in semiconductors for use in telecommunication, networking, storage and graphic industry
Creating the marketing plans
Monitor current market trends and opportunities
Competitive analysis of ASIC/semiconductor design services marketplace
Meet different customers worldwide to establish partnerships with ASIC/semiconductor associations and vendors, participate in trade shows, electronic exhibitions and present company services and products to different global customers
Responsible for the sales forecast and growth of company business multifold
Analyze new business opportunities to win ASIC Design contracts evaluate marketing opportunities for company services and product portfolios
[Two (2) years] - Two (2) years of experience must include two (2) years of experience in: Simaccel, Logic Analyzers/Oscilloscopes, VCS Simulation, Palladium Emulators. Employer will conduct background check and reference check
Job Site :
San Diego, CA. Job may involve working at various unanticipated locations throughout the United States. Travel required to the extent of relocating to various unanticipated locations throughout the United States. Please send resumes referencing the aforementioned job title and reference number to Sivaltech Inc. 6170 Cornerstone Ct. E, Ste 260, San Diego CA 92121
